ESP32-P4 SIMD Explained
Introduction N.B. - This article is for programmers who are familiar with SIMD. Like the ESP32-S3 before it, the ESP32-P4 includes SIMD instructions - Espressif calls them 'PIE' - processor instruction extensions. Before getting into the details of the P4, it's necessary to go over the history of the ESP32 family. The original ESP32, ESP32-S2 and ESP32-S3 all use Cadence's Xtensa LX CPUs. The release of the ESP32-C3 marked a turning point for Espressif with the use of RISC-V CPUs (no license fee). The ESP32-S3 is the last MCU in their lineup to use an Xtensa CPU. Espressif decided to add SIMD instructions (PIE) to the S3 to support more advanced imaging and machine learning tasks. The PIE instructions on the ESP32-S3 look a lot like Cadence's other SIMD instruction sets on their other CPUs. The ESP32-P4 however, has two 32-bit RISC-V CPUs inside. The RISC-V is an open source CPU design that is unrelated to Cadence's Xtensa CPUs. RISC-V's instruction set has ...